For our first RISC-V Meetup of 2023, we have a report and tutorial on an attempt to create the world’s smallest RISC-V based AI processor.

Speakers

  • Ren Chen, Ethan Lim, Amdadullah Md, Isaac Whale and Daniel Zelinka, University of Southampton
  • Nandni Jamnadas, Embecosm

Agenda

6:00pm - Event starts
8:00pm - Event ends

Synopsis

For our first RISC-V Meetup of 2023, we have a report on an attempt to create the world’s smallest RISC-V based AI processor and a tutorial on how to add a builtin function to GCC for RISC-V.

Creating the world’s smallest RISC-V based AI processor

Ren Chen, Ethan Lim, Amdadullah Md, Isaac Whale and Daniel Zelinka, University of Southampton

In previous years, this group has heard about the work of Southampton students developing small extensions to RISC-V to improve the performance of AI inference in low power contexts. This earlier work used standard RISC-V cores under development by the OpenHW Group. The work was carried out as group design projects of the MSc in Computer Systems Engineering.

For this year’s project we have attempted to combine the world’s smallest RISC-V Core, SERV, with our small AI extensions. The goal is to create what could be the world’s smallest RISC-V based AI processor. Suitable for use in very small, low power applications or to explore what is possible with massively parallel simple AI nodes at the edge.

But this is not just a talk about a project to create a novel AI processor. It is also a talk about how a project working to a tight timescale with demanding deliverables can go wrong, and what we did to rescue it and get useful results that will serve as a starting point for future projects.

Tutorial: Adding builtin functions to GCC for RISC-V

Nandni Jamnadas, Embecosm

Many low level features of architectures are implemented in GCC as builtin functions. Builtin functions look superficially like any C function, but are in fact intrinsic to the compiler and represented as patterns to be matched in the machine description. Builtin functions are often used to access unique functionality of individual machine instructions, and , being integrated within the compiler, they are more efficient than using simple inline assembly code. For RISC-V, they offer an excellent way to expose the functionality of instruction set extensions to the C/C++ programmer.

In this tutorial, Nandni Jamnadas will explain how builtin functions are created in GCC, using examples from GCC for the OpenHW Group’s CV32E40Pv2 RISC-V core.

About the speakers

Ren Chen, Ethan Lim, Amdadullah Md, Isaac Whale and Daniel Zelink are MSc students at the University of Southampton. Their project was supervised by Prof Mark Zwolinski and Dr Mark Vousden of the University of Southampton. The industry advisors were Olof Kindgren, Jeremy Bennett and Will Jones.

Nandni Jamnadas is a member of the Embecosm GNU compiler team, and also serves as the lead for the CORE-V GNU tool chain project. She is a UK Electronics Skills Foundation Scholar from Royal Holloway College, University of London.

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COVID-19

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This event is brought to you by: BCS Open Source specialist group

London Open Source Meetup for RISC-V
Date and time
Monday 16 January, 6:00pm - 8:00pm
Location
BCS, The Chartered Institute for IT
Ground Floor, 25 Copthall Avenue
London
EC2R 7BP
Price
This event is sold out